{"id":2107,"date":"2021-01-18T18:57:31","date_gmt":"2021-01-18T16:57:31","guid":{"rendered":"http:\/\/journals.khnu.km.ua\/vestnik\/?p=2107"},"modified":"2021-04-01T12:31:06","modified_gmt":"2021-04-01T09:31:06","slug":"%d1%83%d0%bd%d1%96%d0%b2%d0%b5%d1%80%d1%81%d0%b0%d0%bb%d1%8c%d0%bd%d0%b8%d0%b9-%d1%80%d0%b5%d0%b3%d1%96%d1%81%d1%82%d1%80-%d0%bd%d0%b0-%d0%bf%d0%bb%d1%96%d1%81","status":"publish","type":"post","link":"https:\/\/journals.khnu.km.ua\/vestnik\/?p=2107","title":{"rendered":"\u0423\u043d\u0456\u0432\u0435\u0440\u0441\u0430\u043b\u044c\u043d\u0438\u0439 \u0440\u0435\u0433\u0456\u0441\u0442\u0440 \u043d\u0430 \u043f\u043b\u0456\u0441"},"content":{"rendered":"

\u0423\u041d\u0406\u0412\u0415\u0420\u0421\u0410\u041b\u042c\u041d\u0418\u0419 \u0420\u0415\u0413\u0406\u0421\u0422\u0420 \u041d\u0410 \u041f\u041b\u0406\u0421<\/p>\n

UNIVERSAL REGISTER ON FPGA<\/p>\n

<\/a> \u0421\u0442\u043e\u0440\u0456\u043d\u043a\u0438: 188-191. \u041d\u043e\u043c\u0435\u0440: \u21162, 2019 (271)<\/strong>
\n\u0410\u0432\u0442\u043e\u0440\u0438:<\/strong>
\n\u0414. \u0412. \u0413\u0410\u0412\u0420\u0406\u041b\u041e\u0412, \u0410. \u042e. \u0412\u041e\u041b\u041e\u0412\u0418\u041a, \u041d. \u041c. \u0413\u0410\u0412\u0420\u0406\u041b\u041e\u0412\u0410,
\n\u041d. \u0412. \u041a\u041e\u0424\u0410\u041d\u041e\u0412\u0410, \u0414. \u0412. \u042f\u0420\u041e\u0412\u0418\u0419
\n\u0412\u0456\u043d\u043d\u0438\u0446\u044c\u043a\u0438\u0439 \u043d\u0430\u0446\u0456\u043e\u043d\u0430\u043b\u044c\u043d\u0438\u0439 \u0442\u0435\u0445\u043d\u0456\u0447\u043d\u0438\u0439 \u0443\u043d\u0456\u0432\u0435\u0440\u0441\u0438\u0442\u0435\u0442
\nD. V. HAVRILOV, A. Y. VOLOVYK, N. M. HAVRILOVA, N. V. KOFANOVA, D. V. YAROVYI
\nVinnytsia National Technical University
\nDOI:<\/strong> https:\/\/www.doi.org\/10.31891\/2307-5732-2019-271-2-188-191<\/a>
\n\u0420\u0435\u0446\u0435\u043d\u0437\u0456\u044f\/Peer review :<\/strong> 08.02.2019 \u0440.
\n\u041d\u0430\u0434\u0440\u0443\u043a\u043e\u0432\u0430\u043d\u0430\/Printed :<\/strong> 10.04.2019 \u0440.<\/p>\n

\u0410\u043d\u043e\u0442\u0430\u0446\u0456\u044f \u043c\u043e\u0432\u043e\u044e \u043e\u0440\u0438\u0433\u0456\u043d\u0430\u043b\u0443<\/strong><\/p>\n

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\n\u041a\u043b\u044e\u0447\u043e\u0432\u0456 \u0441\u043b\u043e\u0432\u0430:<\/strong> \u0443\u043d\u0456\u0432\u0435\u0440\u0441\u0430\u043b\u044c\u043d\u0438\u0439 \u0440\u0435\u0433\u0456\u0441\u0442\u0440, \u00a0\u0440\u0435\u0432\u0435\u0440\u0441\u0438\u0432\u043d\u0438\u0439 \u0440\u0435\u0433\u0456\u0441\u0442\u0440 \u0434\u043e\u0432\u0456\u043b\u044c\u043d\u043e\u0457 \u0440\u043e\u0437\u0440\u044f\u0434\u043d\u043e\u0441\u0442\u0456, \u0433\u043d\u0443\u0447\u043a\u0456 \u0441\u0438\u0441\u0442\u0435\u043c\u0438 \u0441\u0442\u0435\u0436\u0435\u043d\u043d\u044f, \u0456\u043d\u0442\u0435\u0433\u0440\u0430\u043b\u044c\u043d\u0456 \u043c\u0456\u043a\u0440\u043e\u0441\u0445\u0435\u043c\u0438 \u0436\u043e\u0440\u0441\u0442\u043a\u043e\u0457 \u043b\u043e\u0433\u0456\u043a\u0438, \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043e\u0432\u0430\u043d\u0456 \u043b\u043e\u0433\u0456\u0447\u043d\u0456 \u0456\u043d\u0442\u0435\u0433\u0440\u0430\u043b\u044c\u043d\u0456 \u0441\u0445\u0435\u043c\u0438, Quartus, Altera, Intel.<\/p>\n

\u0420\u043e\u0437\u0448\u0438\u0440\u0435\u043d\u0430 \u0430\u043d\u043e\u0442\u0430\u0446\u0456\u044f \u0430\u043d\u0433\u043b\u0456\u0439\u0441\u044c\u043a\u043e\u044e \u043c\u043e\u0432\u043e\u044e<\/strong><\/p>\n

In this article, we consider the proposed new circuit decision of the universal register on the FPGA, which allows to perform functions of successive, parallel, serial parallel and parallel-sequential registers, and also provide the modes of disconnection of inputs and outputs from the general information bus, the switching functions of reception \/ transmission of information in the general tire. The reversible registers of arbitrary bit displacement without changing the source code at the reverse point, which allows the creation of flexible monitoring systems based on standard integrated circuits of rigid logic. The results of modelling of the universal shift register on the FPGA in the software of CAD Altera Quartus II with time charts are presented.
\nKeywords:<\/strong> universal register, reverse register of arbitrary digit capacity, flexible tracking systems, hard logic integrated circuits, programmable logic integrated circuits, Quartus, Altera, Intel.<\/p>\n

References<\/strong><\/p>\n

    \n
  1. Novikov Ju.V. Osnovy cifrovoj shemotehniki. Bazovye jelementy i shemy. Metody proektirovanija \/ Jurij Vital’evich Novikov. \u2013 M. : Mir, 2001. \u2013 379 s.<\/li>\n
  2. Havrilov D. V. Laboratornyi praktykum z doslidzhennia tsyfrovykh prystroiv na osnovi SAPR MAX+PLUS II : navchalnyi posibnyk \/ Dmytro Volodymyrovych Havrilov, Viktor Leonidovych Kofanov, Oleksandr Volodymyrovych Osadchuk. \u2013 Vinnytsia : UNIVERSUM-Vinnytsia, 2006. \u2013 200 s.<\/li>\n
  3. Havrilov D. V. Proektuvannia tsyfrovykh prystroiv na osnovi SAPR Quartus II : navchalnyi posibnyk \/ Dmytro Volodymyrovych Havrilov, Viktor Leonidovych Kofanov, Oleksandr Volodymyrovych Osadchuk. \u2013 Vinnytsia : VNTU, 2009. \u2013 164 s.<\/li>\n
  4. Zubchuk V. I. Spravochnik po cifrovoj shemotehnike \/ Viktor Ivanovich Zubchuk, Vitalij Petrovich Sigorskij, Anatolij Nikolaevich Shkuro. \u2013 K. : Tjehnika, 1990. \u2013 448 s.<\/li>\n
  5. 108579 Ukraina, MPK H03M 13\/00, H03M 7\/00. Deshyfrator semysehmentnoho kodu v unitarnyi \/ Basych B. V., Havrilov D. V., Bielov O. E., Sytai Yu. V. ; vlasnyk Vinnytskyi natsionalnyi tekhnichnyi universytet. \u2013 \u2116 u201600023 ; zaiavl. 04.01.2016 ; opubl. 25.07.2016, biul. \u2116 14. \u2013 7 s.<\/li>\n
  6. Havrilov D. V. Osnovy komp`iuternoho proektuvannia ta modeliuvannia REA. Chastyna 1 : laboratornyi praktykum \/ D. V. Havrilov, O. V. Osadchuk, O. S. Zviahin. \u2013 Vinnytsia : VNTU, 2015. \u2013 99 s.<\/li>\n
  7. Havrilov D. V. Osnovy komp`iuternoho proektuvannia ta modeliuvannia REA. Chastyna 2 : laboratornyi praktykum \/ D. V. Havrilov, O. S. Zviahin, O. V. Osadchuk, A. Yu. \u2013 Vinnytsia : VNTU, 2017. \u2013 104 s.<\/li>\n
  8. Jubin Mitra An FPGA-Based Phase Measurement System \/ Jubin Mitra, Tapan K. Nayak \/\/ IEEE Transactions on Very Large Scale Integration (VLSI) Systems. \u2013 2018. \u2013 Vol. 26. \u2013 Iss. 1. \u2013 P. 133\u2013142. \u2013 DOI: 10.1109\/TVLSI.2017.2758807.<\/li>\n<\/ol>\n","protected":false},"excerpt":{"rendered":"

    \u0423\u041d\u0406\u0412\u0415\u0420\u0421\u0410\u041b\u042c\u041d\u0418\u0419 \u0420\u0415\u0413\u0406\u0421\u0422\u0420 \u041d\u0410 \u041f\u041b\u0406\u0421 UNIVERSAL REGISTER ON FPGA \u0421\u0442\u043e\u0440\u0456\u043d\u043a\u0438: 188-191. \u041d\u043e\u043c\u0435\u0440: \u21162, 2019 (271) \u0410\u0432\u0442\u043e\u0440\u0438: \u0414. \u0412. \u0413\u0410\u0412\u0420\u0406\u041b\u041e\u0412, \u0410. \u042e. \u0412\u041e\u041b\u041e\u0412\u0418\u041a, \u041d. \u041c. \u0413\u0410\u0412\u0420\u0406\u041b\u041e\u0412\u0410, \u041d. \u0412. \u041a\u041e\u0424\u0410\u041d\u041e\u0412\u0410, \u0414. \u0412. \u042f\u0420\u041e\u0412\u0418\u0419 \u0412\u0456\u043d\u043d\u0438\u0446\u044c\u043a\u0438\u0439 \u043d\u0430\u0446\u0456\u043e\u043d\u0430\u043b\u044c\u043d\u0438\u0439 \u0442\u0435\u0445\u043d\u0456\u0447\u043d\u0438\u0439 \u0443\u043d\u0456\u0432\u0435\u0440\u0441\u0438\u0442\u0435\u0442 D. V. HAVRILOV, A. Y. VOLOVYK, N. M. HAVRILOVA, N. V. KOFANOVA, D. V. YAROVYI Vinnytsia National Technical University DOI: https:\/\/www.doi.org\/10.31891\/2307-5732-2019-271-2-188-191 […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":[],"categories":[22],"tags":[],"_links":{"self":[{"href":"https:\/\/journals.khnu.km.ua\/vestnik\/index.php?rest_route=\/wp\/v2\/posts\/2107"}],"collection":[{"href":"https:\/\/journals.khnu.km.ua\/vestnik\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/journals.khnu.km.ua\/vestnik\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/journals.khnu.km.ua\/vestnik\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/journals.khnu.km.ua\/vestnik\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=2107"}],"version-history":[{"count":3,"href":"https:\/\/journals.khnu.km.ua\/vestnik\/index.php?rest_route=\/wp\/v2\/posts\/2107\/revisions"}],"predecessor-version":[{"id":5318,"href":"https:\/\/journals.khnu.km.ua\/vestnik\/index.php?rest_route=\/wp\/v2\/posts\/2107\/revisions\/5318"}],"wp:attachment":[{"href":"https:\/\/journals.khnu.km.ua\/vestnik\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=2107"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/journals.khnu.km.ua\/vestnik\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=2107"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/journals.khnu.km.ua\/vestnik\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=2107"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}